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1 ? x9408 low noise/low power/2-wire bus quad digitally controlled (xdcp?) potentiometers description the x9408 integrates four digi tally controlled potentiometers (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 63 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. power-up recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? four potentiometers in one package ? 64 resistor taps per potentiometer ? 2-wire serial interface ? wiper resistance, 40 typical at 5v ? four nonvolatile data registers for each pot ? nonvolatile storage of wiper position ? standby current < 1a max (total package) ?v cc = 2.7v to 5.5v operation v+ = 2.7v to 5.5v v- = -2.7v to -5.5v ?10k , 2.5k end to end resistances ? high reliability ? endurance?100,000 data changes per bit per register ? register data retention?100 years ? 24 ld soic, 24 ld tssop, 24 ld pdip packages ? pb-free (rohs compliant) block diagram interface and control circuitry scl sda a0 a1 a2 a3 r0 r1 r2 r3 wiper counter register (wcr) resistor array pot 1 v h1 /r h1 v l1 /r l1 r0 r1 r2 r3 wiper counter register (wcr) v h0 /r h0 v l0 /r l0 data 8 v w0 /r w0 v w1 /r w1 r0 r1 r2 r3 resistor array v h2 /r h2 v l2 /r l2 v w2 /r w2 r0 r1 r2 r3 resistor array v h3 /r h3 v l3 /r l3 v w3 /r w3 wiper counter register (wcr) wiper counter register (wcr) pot 3 pot 2 wp pot 0 v cc v ss v+ v- caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2005, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. data sheet fn8191.4 january 15, 2009
2 fn8191.4 january 15, 2009 ordering information part number part marking v cc limits (v) potentiometer organization (k ) temp range (c) package x9408ys24* x9408ys 5 10% 2.5 0 to +70 24 ld soic (300 mil) x9408ys24i* x9408ys i -40 to +85 24 ld soic (300 mil) X9408YV24* x9408yv 0 to +70 24 ld tssop (4.4mm) X9408YV24z* (note) x9408yv z 0 to +70 24 ld tssop (4.4mm) (pb-free) X9408YV24i* x9408yv i -40 to +85 24 ld tssop (4.4mm) X9408YV24iz* (note) x9408yv z i -40 to +85 24 ld tssop (4.4mm) (pb-free) x9408ws24* x9408ws 10 0 to +70 24 ld soic (300 mil) x9408ws24i* x9408ws i -40 to +85 24 ld soic (300 mil) x9408wv24* x9408wv 0 to +70 24 ld tssop (4.4mm) x9408wv24z* (note) x9408wv z 0 to +70 24 ld tssop (4.4mm) (pb-free) x9408wv24i* x9408wv i -40 to +85 24 ld tssop (4.4mm) x9408wv24iz* (note) x9408wv z i -40 to +85 24 ld tssop (4.4mm) (pb-free) x9408ys24-2.7* x9408ys f 2.7 to 5.5 2.5 0 to +70 24 ld soic (300 mil) x9408ys24i-2.7* x9408ys g -40 to +85 24 ld soic (300 mil) X9408YV24-2.7* x9408yv f 0 to +70 24 ld tssop (4.4mm) X9408YV24z-2.7* (note) x9408yv z f 0 to +70 24 ld tssop (4.4mm) (pb-free) X9408YV24i-2.7* x9408yv g -40 to +85 24 ld tssop (4.4mm) X9408YV24iz-2.7t1 (note) x9408yv z g -40 to +85 24 ld tssop (4.4mm) tape and reel (pb-free) x9408ws24-2.7* x9408ws f 10 0 to +70 24 ld soic (300 mil) x9408ws24i-2.7* x9408ws g -40 to +85 24 ld soic (300 mil) x9408ws24iz-2.7* (note) x9408ws z g -40 to +85 24 ld soic (300 mil) (pb-free) x9408wv24-2.7* x9408wv f 0 to +70 24 ld tssop (4.4mm) x9408wv24z-2.7* (note) x9408wv z f 0 to +70 24 ld tssop (4.4mm) (pb-free) x9408wv24i-2.7* x9408wv g -40 to +85 24 ld tssop (4.4mm) x9408wv24iz-2.7* (note) x9408wv z g -40 to +85 24 ld tssop (4.4mm) (pb-free) *add "t1" suffix for tape and reel. **add "t1" suffix for tape and reel.please refer to tb347 for details on reel specification s. note: these intersil pb-free plastic packaged pr oducts employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. x9408
3 fn8191.4 january 15, 2009 pin descriptions host interface pins serial clock (scl) the scl input is used to clock data into and out of the x9408. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire- ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical va lues, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. device address (a 0 - a 3 ) the address inputs are used to set the least significant 4 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9408. a maximum of 16 devices may occupy the 2-wire serial bus. potentiometer pins v h /r h (v h0 /r h0 - v h3 /r h3 ), v l /r l (v l0 /r l0 - v l3 /r l3 ) the v h /r h and v l /r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. v w /r w (v w0 /r w0 ? v w3 /r w3 ) the wiper outputs are equivalent to the wiper output of a mechanical potentiometer. hardware write protect input (wp) the wp pin when low prevents nonvolatile writes to the data registers. analog supplies v+, v- the analog supplies v+, v- are the supply voltages for the xdcp analog section. pin assignments pinouts x9408 (24 ld dip/soic) top view x9408 (24 ld tssop) top view symbol description scl serial clock sda serial data a0-a3 device address v h0 /r h0 - v h3 /r h3 , v l0 /r l0 - v l3 /r l3 potentiometer pins (terminal equivalent) v w0 /r w0 - v w3 /r w3 potentiometer pins (wiper equivalent) wp hardware write protection v+,v- analog supplies v cc system supply voltage v ss system ground nc no connection 1 2 3 4 5 6 7 8 9 10 11 12 v cc v l0 /r l0 v h0 /r h0 v w0 /r w0 a 2 wp sda a 1 v l1 /r l1 v h1 /r h1 v w1 /r w1 v ss 16 17 18 19 20 21 22 23 24 15 14 13 v+ v h3 /r h3 v w3 /r/r h1 a 0 nc scl v h2 /r h2 v w2 /r w2 v- v l3 /r l3 a 3 v l2 /r l2 1 2 3 4 5 6 7 8 9 10 11 12 sda a 1 v l1 /r l1 v h1 /r h1 v w1 /r w1 v ss v- v w2 /r w2 v h2 /r h2 v l2 /r l2 scl a 3 16 17 18 19 20 21 22 23 24 15 14 13 wp v w0 /r w0 v h0 /r h0 v l0 /r l0 v cc v l3 /r l3 v w3 /r w3 a 0 nc a 2 v+ v h3 /r h3 x9408
4 fn8191.4 january 15, 2009 principals of operation the x9408 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the xdcp potentiometers. serial interface the x9408 supports a bidirect ional bus oriented protocol. the protocol defines any devic e that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the x9408 will be considered a slave device in all applications. clock and data conventions data states on the sda line can change only during scl low periods (t low ). sda state changes during scl high are reserved for indicating start and stop conditions. start condition all commands to the x9408 are preceded by the start condition, which is a high to low transition of sda while scl is high (t high ). the x9408 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. acknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either t he master or the slave, will release the sda bus after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line lo w to acknowledge that it successfully received th e eight bits of data. the x9408 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the x9408 will respond with a final acknowledge. array description the x9408 is comprised of four resistor arra ys. each array contains 63 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixty-four switches. the wcr may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the wcr. these data registers and the wcr can be read and wri tten by the host system. device addressing following a start condition t he master must output the address of the slave it is acce ssing. the most significant four bits of the slave address are the device type identifier (refer to figure 1 below). for the x9408 this is fixed as 0101[b]. the next four bits of the slave address are the device address. the physical device address is defined by the state of the a 0 - a 3 inputs. the x9408 compares the serial data stream with the address input st ate; a successful compare of all four address bits is required for the x9408 to respond with an acknowledge. the a 0 - a 3 inputs can be actively driven by cmos input signals or tied to v cc or v ss . acknowledge polling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the nonvolatile write command the x9408 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the devic e slave address. if the x9408 is still busy with the write oper ation no ack will be returned. if the x9408 has completed t he write operation an ack will be returned and the master can then proceed with the next operation. 1 00 a3 a2 a1 a0 device type identifier device address 1 figure 1. slave address x9408
5 fn8191.4 january 15, 2009 flow 1. ack polling sequence instruction structure the next byte sent to the x9408 contains the instruction and register pointer information. the four most significant bits are the instruction. the next four bits point to one of the two pots and when applicable they point to one of four associated registers. the format is shown in figure 2. the four high order bits define the instruction. the next two bits (r1 and r0) select one of the four registers that is to be acted upon when a register ori ented instruction is issued. the last bits (p1, p0) select which one of the four potentiometers is to be affected by the instruction. four of the nine instructions end with the transmission of the instruction byte. the basic sequence is illustrated in figure 3. these two-byte instructions exchange data between the wiper counter register and one of the data registers. a transfer from a data register to a wiper counter register is essentially a write to a static ram. the response of the wiper to this action will be delayed t wrl . a transfer from the wiper counter register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. four instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9408; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: read wiper counter register (read the current wiper position of the selected pot), write wiper counter register (change current wiper position of the selected pot), read data regi ster (read the c ontents of the selected nonvolatile register) and write data register (write a new value to the selected data register). the sequence of operations is shown in figure 4. non-volatile write command completed enter ack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed i1 i2 i3 i0 r1 r0 p1 p0 wiper counter register select instructions register select figure 2. instruction byte format s t a r t 0101a3a2a1a0 a c k i3 i2 i1 i0 r1 r0 p1 p0 a c k scl sda s t o p figure 3. two-byte instruction sequence x9408
6 fn8191.4 january 15, 2009 the increment/decrement command is different from the other commands. once the command is issued and the x9408 has responded with an a cknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figures 5 and 6 respectively. table 1. instruction set note: (7)1/0 = data is one or zero instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 p 1 p 0 read wiper counterregister 1 0 0 1 0 0 p 1 p 0 read the contents of the wiper counter register pointed to by p 1 - p 0 write wiper counterregister 1 0 1 0 0 0 p 1 p 0 write new value to the wiper counter register pointed to by p 1 - p 0 read data register 1 0 1 1 r 1 r 0 p 1 p 0 read the contents of the data register pointed to by p 1 - p 0 and r 1 - r 0 write data register 1 1 0 0 r 1 r 0 p 1 p 0 write new value to the data register pointed to by p 1 - p 0 and r 1 - r 0 xfr data register to wiper counter register 1101r 1 r 0 p 1 p 0 transfer the contents of the data register pointed to by p 1 - p 0 and r 1 - r 0 to its associated wiper counter register xfr wiper counter register to data register 1110r 1 r 0 p 1 p 0 transfer the contents of the wiper counter register pointed to by p 1 - p 0 to the data register pointed to by r 1 - r 0 global xfr data registers to wiper counter registers 0001r 1 r 0 0 0 transfer the contents of the data registers pointed to by r 1 - r 0 of all four pots to their respective wiper counter registers global xfr wiper counter registers to data register 1000r 1 r 0 0 0 transfer the contents of both wiper counter registers to their respective data registers pointed to by r 1 - r 0 of all four pots increment/decrement wiper counter register 00100 0p 1 p 0 enable increment/decrement of the wiper counter register pointed to by p 1 - p 0 s t a r t 0 1 0 1 a3 a2 a1 a0 a c k i3 i2 i1 i0 r1 r0 p1 p0 a c k scl sda s t o p a c k 0 0 d5 d4 d3 d2 d1 d0 figure 4. three-byte instruction sequence s t a r t 0 1 0 1 a3 a2 a1 a0 a c k i3 i2 i1 i0 r0 p1 p0 a c k scl sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n r1 figure 5. increment/decrement instruction sequence x9408
7 fn8191.4 january 15, 2009 scl sda v w /r w inc/dec cmd issued voltage out t wrid figure 6. increment/decrement timing limits scl from data output 1 89 start acknowledge master from transmitter data output from receiver figure 7. acknowledge respnse from receiver x9408
8 fn8191.4 january 15, 2009 detailed operation all xdcp potentiometers shar e the serial interface and share a common architecture. each potentiometer has a wiper counter register and four data registers. a detailed discussion of the register organization and array operation follows. wiper counter register the x9408 contains four wipe r counter registers, one for each xdcp potentiometer. the wiper counter register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load); it can be modified one step at a time by the increment/ decrement instruction. finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wcr is a volatile register; that is, its contents are lost when the x9408 is powered-down. although the register is automatically loaded with the va lue in r0 upon power-up, it should be noted this may be different from the value present at power-down. data registers each potentiometer has four nonvolatile data registers. these can be read or written directly by the host and data can be transferred between any of the four data registers and the wcr. it should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not r equire storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. register descriptions four 6-bit data registers for each xdcp. (sixteen 6-bit registers in total). {d5~d0}: these bits are for general purpose not volatile data stora ge or for storage of up to four different wiper values. the contents of data register 0 are automatically moved to the wiper counter register on power-up. serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h v l /r l v w /r w if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c o u n t e r d e c o d e (wcr) figure 8. detailed potentiometer block diagram table 2. date registers, (6-bit), nonvolatile d5 d4 d3 d2 d1 d0 nv nv nv nv nv nv (msb) (lsb) x9408
9 fn8191.4 january 15, 2009 one 6-bit wiper counter register for each xdcp. (four 6-bit registers in total.) {d5~d0}: these bits specify the wiper position of the respective xdcp. the wiper counter register is loaded on power-up by the value in data register 0. the contents of the wcr can be loaded from any of the other data register or directly. the contents of the wcr can be saved in a dr. instruction format notes: 1. ?mack?/?sack?: stands for the acknowledge sent by the master/slave. 2. ?a3 ~ a0?: stands for the device addresses sent by the master. 3. ?x?: indicates that it is a ?0? for testing pur pose but physically it is a ?don?t care? condition. 4. ?i?: stands for the increment operation, sda held high during active scl phase (high). 5. ?d?: stands for the decrement operation, sda held low during active scl phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) xfr data register (dr) to wiper counter register (wcr) table 3. wiper counter re gister, (6-bit), volatile wp5 wp4 wp3 wp2 wp1 wp0 vvvvvv (msb) (lsb) s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k wiper position (sent by slave on sda) m a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 0 0 1 0 0 p1 p0 0 0 wp 5 wp 4 wp 3 wp 2 wp 1 wp 0 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k wiper position (sent by master on sda) s a c k s t o p 0101a3a2a1a0 101000p1p0 00w p5 w p4 w p3 w p2 w p1 w p0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k wiper position/data (sent by slave on sda) m a c k s t o p 0101a3a2a1a0 1011r1r0p1p0 00w p5 w p4 w p3 w p2 w p1 w p0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k wiper position/data (sent by master on sda) s a c k s t o p high-voltage write cycle 0101a3a2a1a0 1100r1r0p1p0 00w p5 w p4 w p3 w p2 w p1 w p0 s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k s t o p 0101a3a2a1a0 1 1 0 1 r1r0p1p0 x9408
10 fn8191.4 january 15, 2009 write wiper counter register (wcr) to data register (dr) increment/decrement wiper counter register (wcr) global xfr data register (dr) to wiper counter register (wcr) global xfr wiper counter register (wcr) to data register (dr) symbol table guidelines for calculating typical values of bus pull-up resistors s t a r t device type identifier device addresses s a c k instruction opcode dr and wcr addresses s a c k s t o p high-voltage write cycle 0 1 0 1 a3 a2 a1 a0 1 1 1 0 r1 r0 p1 p0 s t a r t device type identifier device addresses s a c k instruction opcode wcr addresses s a c k increment/decrement (sent by master on sda) s t o p 0101a3a2a1a0 0 0 1 000p1p0 i/di/d. . . .i/di/d s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p 0 1 0 1 a3a2a1a0 0 0 0 1 r1r0 0 0 s t a r t device type identifier device addresses s a c k instruction opcode dr addresses s a c k s t o p high-voltage write cycle 0 1 0 1 a3a2a1a0 1 0 0 0 r1r0 0 0 waveform inputs outputs must be steady will be steady may change from lo w to high will change from lo w to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance ( ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k x9408
11 fn8191.4 january 15, 2009 absolute maximum rati ngs thermal information supply voltage (v cc limits) x9408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% x9408-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v voltage on sda, scl any address input with respect to v ss : . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v voltage on v+ (referenced to v ss ). . . . . . . . . . . . . . . . . . . . . . .10v voltage on v- (referenced to v ss ) . . . . . . . . . . . . . . . . . . . . . . -10v (v+) - (v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma any vh/rh, vl/rl, vw/rw . . . . . . . . . . . . . . . . . . . . . . . . v- to v+ temperature under bias . . . . . . . . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. analog specifications (over recommended operating conditions unless otherwise stated. ) symbol parameter test condition limits min (note 6) typ (note 4) max (note 6) unit r total end to end resistance tolerance -20 +20 % power rating +25c, each pot 50 mw r w wiper resistance i w = (v h - v l )/r total @ v+, v- = 3v 150 250 i w = (v h - v l )/r total @ v+, v- = 5v 40 100 v v + voltage on v+ pin x9408 +4.5 +5.5 v x9408-2.7 +2.7 +5.5 v v - voltage on v- pin x9408 -5.5 -4.5 v x9408-2.7 -5.5 -2.7 v term voltage on any v h /r h , v l /r l or v w /r w pin v- v+ v noise ref: 1khz -120 dbv resolution (note 4) 1.6 % absolute linearity (note 1) v(v wn /r wn ) (actual) - v(v wn /r wn ) (expected) (note 4) -1 +1 mi (note 3) relative linearity (note 2) v(v w(n+1) /r w(n+1) ) - [v(v w(n) /r w(n) ) + mi] (note 4) -0.2 +0.2 mi (note 3) temperature coefficient of r total (note 4) 300 ppm/c ratiometric temperature coefficient (note 4) 20 ppm/c c h /c l /c w potentiometer capacitances see macro model 10/10/25 pf i al v h /r h , v l /r l , v w /r w leakage current v in = v- to v+. device is in stand- by mode. 0.1 10 a x9408
12 fn8191.4 january 15, 2009 notes: 1. absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 2. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 3. mi = rtot/63 or [v(v h /r h ) - v(v l /r l )]/63, single pot endurance and data retention capacitance power-up timing notes: 4. limits should be considered typi cal and are not production tested. 5. t pur and t puw are the delays required from the ti me the third (last) power supply (v cc , v+ or v-) is stable until the specific instruction can be issued 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. dc electrical specifications (over recommended operating condit ions unless otherwise stated. ) symbol parameter test conditions limits min (note 6) typ (note 4) max (note 6) unit i cc1 v cc supply current (nonvolatile write) f scl = 400khz, sda = open, other inputs = v ss 5ma i cc2 v cc supply current (move wiper, write, read) f scl = 400khz, sda = open, other inputs = v ss 250 a i sb v cc current (standby) scl = sda = v cc , addr. = v ss 3a i li input leakage current 10 a i lo output leakage current 10 a v ih input high voltage v cc x 0.7 v cc +0.5 v v il input low voltage ?0.5 v cc x 0.1 v v ol output low voltage i ol = 3ma 0.4 v parameter min unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test test condition typ (note 4) unit c i/o (note 4) input/output capacitance (sda) v i/o = 0v 8 pf c in (note 4) input capacitance (a0, a1, a2, a3, and scl) v in = 0v 6 pf symbol parameter min (note 6) max (note 6) unit t pur (note 5) power-up to initiation of read operation 1 ms t puw (note 5) power-up to initiation of write operation 5 ms t r v cc (note 6) v cc power-up ramp 0.2 50 v/msec x9408
13 fn8191.4 january 15, 2009 power-up requirements (power-up sequencing can affect correct recall of the wiper registers). the preferred power-on sequence is as follows: first v-, then v cc and v+, and then the potentiometer pins, v h /r h , v l /r l , and v w /r w . voltage should not be applied to the potentiometer pins before v+ or v- is applied. the v cc ramp rate specification should be met, and any glitches or slope changes in the v cc line should be held to <100mv if possible. if v cc powers down, it should be held below 0.1v for more than 1 second before powering up again in order for proper wiper register recall. also, v cc should not reverse polarity by more than 0.5v. recall of wiper position will not be complete until v cc , v+ and v- reach their final value. a.c. test conditions equivalent a.c. load circuit circuit #3 spice macro model i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 5v 1533 100pf sda output 10pf v h /r h r total c h 25pf c w c l 10pf v w /r w v l /r l x9408
14 fn8191.4 january 15, 2009 ac timing (over recommended operating condition) high-voltage write cycle timing xdcp timing symbol parameter min (note 5) max (note 5) unit f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r (note 7) scl and sda rise time 300 ns t f (note 7) scl and sda fall time 300 ns t aa scl low to sda data output valid time 900 ns t dh sda data output hold time 50 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1300 ns t su:wpa wp , a0, a1, a2 and a3 setup time 0 ns t hd:wpa wp , a0, a1, a2 and a3 hold time 0ns notes: 7. this parameter is not production tested. parameter established by characterization. symbol parameter typ. (note 4) max. (note 6) unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. (note 5) max. (note 6) unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sck edge (increment/decrement instruction) 10 s x9408
15 fn8191.4 january 15, 2009 timing diagrams start and stop timing g input timing output timing xdcp timing (for all load instructions) t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa scl sda vwx (stop) lsb t wrl x9408
16 fn8191.4 january 15, 2009 xdcp timing (for increment/decrement instruction) write protect and device address pins timing applications information basic configurations of electronic potentiometers scl sda vwx t wrid wiper register addr ess inc/dec inc/dec sda scl ... ... ... wp a0, a1 a2, a3 t su:wpa t hd:wpa (start) (stop) (any instruction) v r +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current x9408
17 fn8191.4 january 15, 2009 application circuits noninverting amplifie r voltage regulator offset voltage adjustment comparator with hysteresis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } x9408
18 fn8191.4 january 15, 2009 application circuits (continued) inverting amplifier equivalent l-r circuit + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c attenuator filter + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) r 2 r 4 all r s = 10k + ? v s r 2 r 1 r c v o x9408
19 fn8191.4 january 15, 2009 plastic packages for in tergrated circuits thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8191.4 january 15, 2009 x9408 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 8 0 8 - rev. 1 4/06

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